Deriving Two-Phase Modules for a Multi-Target Hardware Compiler

This paper adopts the CSP framework for deriving a compilation scheme from a simple imperative language to two-phase modules. Two-phase modules are processes that communicate with one another using two-phase handshake protocols. The two-phase modules generated by our compilation scheme can be implemented as asynchronous or clocked circuits. The derivation techniques have been applied to a concurrent language which is a superset of the language discussed.

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Author and article information

Conference

Publication date: September 1996

Publication date (Print): September 1996

Pages: 1-13

Affiliations

[0001]Oxford University Computing Laboratory

Wolfson Building, Parks Road, Oxford OX1 3QD, UK

[0002]School of Electrical Engineering, Cornell University

Ithaca, NY 14853, USA

[0003]Department of Computing, Imperial College

180 Queen’s Gate, London SW7 2BZ, UK

[0004]Microprocessor Products Group, Intel Corporation

2111 NE 25th Avenue, Mail Stop JF1-81, Hillsboro, Oregon 97124-5961, USA

Article

DOI: 10.14236/ewic/DCC1996.3

SO-VID: 8202ff36-1109-43f6-a8fb-e9876fd8da11

License:

This work is licensed under a Creative Commons Attribution 4.0 Unported License. To view a copy of this license, visit http://creativecommons.org/licenses/by/4.0/

Conference name: Proceedings of the 3rd Workshop on Designing Correct Circuits (DCC96)

Conference acronym: DCC

Conference number: 3

Conference location: Båstad, Sweden

Conference date: 2 - 4 September 1996

Conference sponsor: Electronic Workshops in Computing (eWiC)

Conference theme: Designing Correct Circuits

History

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1477-9358 BCS Learning & Development

Self URI (article page): https://www.scienceopen.com/hosted-document?doi=10.14236/ewic/DCC1996.3

Self URI (journal page): https://ewic.bcs.org/

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Deriving Two-Phase Modules for a Multi-Target Hardware Compiler

Abstract